Dynamic control of switching reference voltage

ABSTRACT

A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don&#39;t result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

FIELD OF THE INVENTION

[0001] This invention relates generally to electronic circuits and moreparticularly to methods and circuits for receiving digital electronicsignals.

BACKGROUND OF THE INVENTION

[0002] Digital electronic signals are used to communicate digitalinformation. This communication may be from on device to another, oneintegrated circuit (or chip) to another, or within an integrated circuititself. In many of these applications, the difference between the avoltage level that denotes a “high” (or logical “1”) and the voltagelevel that denotes a “low” (or logical “0”) has been getting smaller.Designers have chosen these smaller differentials for reasons thatinclude: lower power supply voltages, increasing switching speed,lowering power consumption, and the use of standard bus interfaces thathave defined smaller voltage differentials.

[0003] Unfortunately, these smaller voltage differentials are harder todetect, especially in the presence of noise or other non-idealities onthe signal. Accordingly, there is a need in the art for improvementsthat help with the detection and reception of digital signals havingsmall voltage differentials between logical levels.

SUMMARY OF THE INVENTION

[0004] A reference voltage is moved dynamically towards a voltage levelof the last received value. The movement takes place over apredetermined fraction of a bit time. The amount of movement is limitedso that successive logical values don't result in an unusable referencevoltage level.

[0005] Other aspects and advantages of the present invention will becomeapparent from the following detailed description, taken in conjunctionwith the accompanying drawings, illustrating by way of example theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is voltage vs. time plot of an exemplary input signal, adynamically controlled reference voltage, and a static referencevoltage.

[0007]FIG. 2 is a flowchart illustrating steps to dynamically control areference voltage.

[0008]FIG. 3 is a schematic diagram illustrating a circuit thatdynamically controls a reference voltage.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]FIG. 1 is voltage vs. time plot of an exemplary input signal 102,a dynamically controlled reference voltage 104, and a static referencevoltage 106. In FIG. 1, note how the dynamically controlled referencevoltage 104 moves toward the voltage level of the exemplary input signal102 after each transition of the exemplary input signal 102. Themovement is shown taking place over a period of time that approximatesone-half a bit-time, t_(bit). A bit-time is the normal period of themaximum data frequency. Once the dynamically controlled referencevoltage 104 reaches a predetermined level, it stays approximatelyconstant until another transition takes place on the input signal 102.

[0010] V_(A) and V_(B) illustrate the minimum voltage differentialbetween the input signal 102 and the dynamically controlled referencevoltage 102 shortly after a transition. This minimum voltagedifferential may eventually become smaller as the dynamically controlledreference voltage 104 moves toward the input signal 102, but by then,much of the noise on the input signal 102 has settled out so the inputsignal 102 doesn't cross the dynamically controlled reference voltage104. Note that V_(A) and V_(B) are both larger than the minimum voltagedifferential between the input signal 102 and the static referencevoltage 106 at the same point in time. Accordingly, at this criticaltime shortly after an input signal 102 transition, the noise margin forthe dynamically controlled reference signal 104 is larger than the noisemargin for the static reference signal 106.

[0011] Also note that, as shown in FIG. 1, it takes less time for theinput signal 102 to cross the dynamically controlled reference voltage104 than it does the static reference voltage 106. This is shown as Atin FIG. 1. Since the dynamically controlled reference voltage 104 hasmoved closer to the input signal 102 voltage than the static referencevoltage 106 (which does not move) near the end of each bit-time, aninput signal 102 transition with a non-infinite slope crosses thedynamically controlled reference voltage 104 level sooner than itcrosses the static reference voltage 106 level. This illustrates that aninput signal 102 transition can be detected faster with the dynamicallycontrolled reference voltage 104 than it can be detected with a staticreference voltage 106.

[0012]FIG. 2 is a flowchart illustrating steps to dynamically control areference voltage. In a step 202, an initialization decision is made. Ifthe current state of the input signal is at a high low voltage, flowproceeds to step 214. If the current state of the input signal is a lowvoltage, flow proceeds to step 204. In a step 204, the system waits fora transition. Since it was determined in step 202 that the current stateof the input signal was at a low voltage, or because flow to step 204came from step 216 just after a high-to-low transition, the transitionin step 204 would be a low-to-high transition. After this transition,flow proceeds to step 206. In a step 206, the reference voltage isramped-up from its present voltage to a higher voltage. Flow thenproceeds to step 214.

[0013] In a step 214, the system waits for a transition. Since it wasdetermined in step 202 that the current state of the input signal was ata high voltage, or because low to step 214 came from step 206 just aftera low-to-high transition, the transition in step 214 would be ahigh-to-low transition. After this transition, flow proceeds to step216. In a step 216, the reference voltage is ramped-up from its presentvoltage to a higher voltage. Flow then proceeds to step 204.

[0014]FIG. 3 is a schematic diagram illustrating a circuit thatdynamically controls a reference voltage. In FIG. 3, a resistive laddernetwork 302 provides numerous different voltages to an analogmultiplexer (MUX) 304 via analog signal lines 310. One of these numerousdifferent voltages is selected, according to the digital values oncounter outputs 312, by MUX 304 and outputs a dynamically controlledreference voltage, VREF. Resistive ladder 302 may divide down the supplyvoltages or another reference voltage supplied to it to generate thesedifferent voltages.

[0015] Differential receiver 308 has two inputs, REF and PAD. The PADinput is connected to the input signal being received. The REF input isconnected to the dynamically controlled reference voltage, VREF. If thevoltage on REF is greater than PAD, then differential receiver 308drives signal OUT to a logical “I”. If the voltage on REF is less thanPAD, then differential receiver 308 drives signal OUT to a logical “0”.

[0016] Signal OUT also controls the direction of saturating binarycounter 306. By saturating binary counter it is meant that the counteroutputs 312 of counter 306 does not “rollover” from its lowest value tois highest value when counting down and does not “rollover” from itshighest value to its lowest value when counting up. Instead, the counteroutputs 312 reach these values and hold them until the direction control(UP/DOWN) changes state.

[0017] Counter 306 is clocked by a clock signal CK. CK typically runs ata rate that is much faster than each bit-time so that during the courseof one bit-time, counter 306 could count from its lowest output value toits highest output value and visa-versa.

[0018] To illustrate the operation of the circuit shown in FIG. 3,assume that the PAD signal is at a lower voltage than the lowest analogvoltage generated by resistive ladder 302 which is being output by MUX304 as VREF and that it has been that way long enough for OUT to havecommanded counter 306 to count down for enough time that counter outputs312 have saturated at their lowest value. This is a static state as longas the voltage on PAD does not exceed VREF.

[0019] Now assume that the voltage on PAD changes from a low voltagelevel to a high voltage level similar to one of the changes shown inFIG. 1. This change causes PAD input to differential receiver to behigher than VREF so that differential receiver 308 changes the state ofits output causing counter 306 to begin counting up with each cycle ofCLK. As counter 306 counts up, counter outputs 312 cause MUX 304 tosuccessively select increasing analog voltages generated by resistiveladder 302 with each cycle of CLK and place these successivelyincreasing analog voltages on VREF. This results in a movement of thedynamically controlled reference voltage, VREF, moving towards a voltagelevel of the received voltage level on PAD. This process continues untilcounter outputs 312 saturate at their highest value. At this time, MUX304 is selecting the highest analog voltage generated by resistiveladder 302 and VREF stabilizes at this voltage level until PAD changesto a voltage level lower than VREF. This process is reversed withcounter outputs 312 counting down and VREF successively decreasing whenPAD changes from a high voltage level to a low voltage level similar toone of the changes shown in FIG. 1.

[0020] As shown in FIG. 1, it would be typical for the highest voltagegenerated by resistive ladder 302 to be less than the expected long-termsteady state high voltage on PAD. Likewise, it would be typical for thelowest voltage generated by resistive ladder 302 to be more than theexpected long-term steady state low voltage on PAD. Finally, it wouldalso be typical for CLK to be about 2N times faster than the fastestcycle time of the signal on PAD, there N is the number of inputs to MUX304. This results in a typical transition time for VREF of about ½ abit-time of the input signal on PAD. Note that almost any combination ofCLK frequency and number of inputs, N, could be chosen. Values even aslarge or larger than 1.5 times a bit time or as small or smaller than0.25 a bit time may be desirable depending upon the characteristics ofthe input signal.

[0021] Although a specific embodiment of the invention has beendescribed and illustrated, the invention is not to be limited to thespecific forms or arrangements of parts so described and illustrated.The invention is limited only by the claims.

What is claimed is:
 1. A method, comprising: moving a reference voltagefrom a first voltage level to a second voltage level wherein said secondvoltage level is closer to a received voltage level than said firstvoltage level and wherein said reference voltage is compared to saidreceived voltage level to determine a digital state of said receivedvoltage level.
 2. The method of claim 1 wherein said movement from saidfirst voltage level to said second voltage level takes place over aperiod of time that is on the order of the one-half the minimum timesaid received voltage level is expected to remain in one digital state.3. The method of claim 2 further comprising: moving said referencevoltage from said second voltage level to said first voltage levelwherein said first voltage level is closer to said received voltagelevel than said second voltage level.
 4. A method, comprising: comparinga parameter of an input signal to a parameter of a reference todetermine a logical state of said input signal; and, adjusting saidparameter of said reference to reduce a difference between saidparameter of said reference and said parameter of said input signal. 5.The method of claim 4 wherein said difference between said parameter ofsaid reference and said parameter of said input signal maintains anonzero minimum difference.
 6. A method, comprising: comparing aparameter of an input signal to a parameter of a reference to determinea logical state of said input signal wherein said parameter of saidinput signal has a nominal value representing a logical low and anominal value representing a logical high; and, adjusting said parameterof said reference to reduce a difference between said parameter of saidreference and said parameter of said input signal and said parameter ofsaid reference signal stays between said nominal value representing saidlogical low and said nominal value representing said logical high. 7.The method of claim 6 wherein said parameter of said reference isadjusted over a period of time that greater than 0.25 and less than 1.5times the minimum expected period of time that said input signal willremain in a single logical state.
 8. A method of receiving a digitalsignal, comprising: comparing said digital signal to a referencevoltage; determining when said digital signal has changed from beinggreater than said reference voltage to being less than said referencevoltage; and, reducing said reference voltage after said digital signalhas changed from being greater than said reference voltage to being lessthan said reference voltage.
 9. The method of claim 8 wherein saidreference voltage is reduced over a period of time that is greater thanan expected period of time for said digital signal to change from onedigital state to another.
 10. A method of receiving a digital signal,comprising: comparing said digital signal to a reference voltage;determining when said digital signal has changed from being less thansaid reference voltage to being greater than said reference voltage;and, increasing said reference voltage after said digital signal haschanged from being, less than said reference voltage to being greaterthan said reference voltage.
 11. The method of claim 10 wherein saidreference voltage is increased over a period of time that is greaterthan an expected period of time for said digital signal to change fromone digital state to another.
 12. A method, comprising: adjusting areference between a first nominal reference level and a second nominalreference level; adjusting said reference between said second nominalreference level and said first nominal reference level; comparing asignal to said first nominal reference level when said signal is closerto said first nominal reference level than said second nominal referencelevel; and, comparing said signal to said second nominal reference levelwhen said signal is closer to said second nominal reference level thansaid first nominal reference level.
 13. The method of claim 12 whereinsaid steps of comparing are used to initiate said steps of adjusting sothat said reference becomes closer to said first nominal reference levelafter said signal has crossed said second nominal reference level and sothat said reference becomes closer to said second nominal referencelevel after said signal has crossed said first nominal reference level.14. A method of controlling a reference voltage, comprising: tracking aninput voltage with said reference voltage such that the voltagedifference between an electrical high level and said reference voltageis increased by the change in said input signal as said input signaltransitions from an electrical low level to said electrical high leveland the voltage difference between said electrical high level and saidreference voltage is decreased by increasing said reference voltageafter said input signal transitions.
 15. A method of controlling areference voltage, comprising: tracking an input voltage with saidreference voltage such that the voltage difference between an electricallow level and said reference voltage is increased by the change in saidinput signal as said input signal transitions from an electrical highlevel to said electrical low level and the voltage difference betweensaid electrical low level and said reference voltage is decreased bydecreasing said reference voltage after said input signal transitions.16. An apparatus, comprising: means for tracking an input voltage withsaid reference voltage such that the voltage difference between anelectrical high level and said reference voltage is increased by thechange in said input signal as said input signal transitions from anelectrical low level to said electrical high level and the voltagedifference between said electrical high level and said reference voltageis decreased by increasing said reference voltage after said inputsignal transitions.
 17. An apparatus, comprising: means for tracking aninput voltage with said reference voltage such that the voltagedifference between an electrical low level and said reference voltage isincreased by the change in said input signal as said input signaltransitions from an electrical high level to said electrical low leveland the voltage difference between said electrical low level and saidreference voltage is decreased by decreasing said reference voltageafter said input signal transitions.
 18. A circuit, comprising: meansfor moving a reference voltage from a first voltage level to a secondvoltage level wherein said second voltage level is closer to a receivedvoltage level than said first voltage level and wherein said referencevoltage is compared to said received voltage level to determine adigital state of said received voltage level.
 19. A circuit comprising:a differential receiver that compares an input signal and a referencesignal; and, a reference signal control responsive to said differentialreceiver that adjusts said reference signal over a period of time toapproach said input signal.
 20. The circuit of claim 19 wherein saidreference signal control comprises: a saturating counter wherein a countdirection of said counter is responsive to said differential receiver;and, an analog MUX responsive to said saturating counter that selectsone of a plurality of input voltages and outputs that one of saidplurality of voltages to be used as said reference signal.
 21. Thecircuit of claim 20 wherein said plurality of voltages are generated bya resistive ladder.
 22. The circuit of claim 20 wherein said saturatingcounter is clocked by a clock signal having a period that is much lessthan the minimum expected time for said input signal to remain in onelogical state.